MC100EL33(2008) 데이터 시트보기 (PDF) - ON Semiconductor
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MC100EL33 Datasheet PDF : 10 Pages
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MC10EL33, MC100EL33
Table 1. PIN DESCRIPTION
Pin
Function
CLK, CLK
Reset
Q, Q
VBB
VCC
VEE
EP
ECL Clock Inputs*
ECL Asynch Reset*
ECL Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad must be connected to a
sufficient thermal conduit. Electrically connect to the most
negative supply (GND) or leave unconnected, floating
open.
*Pins will default low when left open.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI VCC
VI VEE
8
V
−8
V
6
V
−6
V
50
mA
100
mA
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
± 0.5
−40 to +85
−65 to +150
190
130
mA
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
41 to 44
185
140
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
41 to 44 ± 5%
129
84
°C/W
°C/W
°C/W
Tsol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
°C
265
qJC
Thermal Resistance (Junction−to−Case)
(Note 1)
DFN8
35 to 40
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
http://onsemi.com
2
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