MAX8772GTL 데이터 시트보기 (PDF) - Maxim Integrated
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MAX8772GTL Datasheet PDF : 47 Pages
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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
PWM Controller for IMVP-6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_ =
1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified. Typical values are at TA = +25°C.)
(Note 4)
PARAMETER
CURRENT LIMIT
Valley Current-Limit Threshold
(Positive)
SYMBOL
CONDITIONS
VLIMIT CSP_ - CSN_
MIN TYP MAX UNITS
18.5
26.5
mV
Valley Current-Limit Threshold
(Negative)
CSP_ - CSN_
-36
-24
mV
Current-Sense Common-Mode
CSP_, CSN_
0
Input Range
Phase 2 Disable Threshold
CSP2
3
GATE DRIVERS
DH_ Gate Driver On-Resistance
RON(DH_)
BST_ – LX_ forced
to 5V
High state (pullup)
Low state (pulldown)
DL_ Gate Driver On-Resistance
High state (pullup)
RON(DL_)
Low state (pulldown)
DH_ Low to DL_ High
15
Driver Propagation Delay
DL_ Low to DH_ High
9
Internal Boost Charging Switch
On-Resistance
VDD to BST_
POWER MONITOR
Power-Monitor Output Voltage for
Typical HFM Conditions
VFB - VGNDS = 1.200V, Σ∆VCS = 30mV
2.04
2
V
VCC - 0.4
V
2.5
Ω
2.5
2.0
Ω
0.5
ns
20
Ω
2.28
V
Power-Monitor Gain Referred to
Feedback Voltage
Σ∆VCS = 30mV
1.70
1.90
V/V
Power-Monitor Gain Referred to
ΣV(CSP_,CSN)
Power-Monitor Load Regulation
LOGIC AND I/O
Logic-Input High Voltage
Low-Voltage Logic-Input High
Low-Voltage Logic-Input Low
VFB - VGNDS = 1.200V
Sourcing: IPOUT = 0 to 500µA
VIH
VIHLV
VILLV
SHDN, DPRSLPVR, rising edge,
hysteresis = 200mV
D0–D6, PSI, DRPSTP
D0–D6, PSI, DRPSTP
70
74
V/V
-6
µV/µA
1.2
2.3
V
0.67
V
0.33
V
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher
than the trip level by 50% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transition-
ing from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ and DH_ pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times may be different due to MOSFET switching speeds.
Note 4: Specifications to TA = -40°C and +105°C are guaranteed by design and are not production tested.
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