A28F010 데이터 시트보기 (PDF) - Intel
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A28F010 Datasheet PDF : 23 Pages
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A28F010
AC CHARACTERISTICS Write Erase Program Operations(1 3)
Versions
Symbol
Characteristic
Notes
28F010-120
Min Max
28F010-150
Unit
Min Max
tAVAV tWC
Write Cycle Time
120
tAVWL tAS
Address Set-Up Time
0
tWLAX tAH
Address Hold Time
2
60
tDVWH tDS Data Set-up Time
50
tWHDX tDH Data Hold Time
10
tWHGL
Write Recovery Time before Read
6
tGHWL
Read Recovery Time before Write
0
tELWL tCS
Chip Enable
Set-Up Time before Write
2
20
150
ns
0
ns
60
ns
50
ns
10
ns
6
ms
0
ms
20
ns
tWHEH tCH
tWLWH tWP
tELEH
Chip Enable Hold Time
Write Pulse Width(2)
Alternative Write(2)
Pulse Width
0
2
80
2
80
0
ns
80
ns
80
ns
tWHWL tWPH Write Pulse Width High
20
tWHWH1
Duration of Programming Operation 4
10
tWHWH2
Duration of Erase Operation
4
95
tVPEL
VPP Set-Up
10
Time to Chip Enable Low
20
ns
10
ms
95
ms
10
ms
NOTES
1 Read timing characteristics during read write operations are the same as during read-only operations Refer to AC Char-
acteristics for Read-Only Operations
2 Chip-Enable Controlled Writes Write operations are driven by the valid combination of Chip-Enable and Write-Enable In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform
3 Rise Fall time s 10 ns
4 The internal stop timer terminates the programming erase operations thereby eliminating the need for a maximum speci-
fication
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Notes
Limits
Min
Typ
Unit
Max
Comments
Chip Erase Time
1346
1
60 Sec Excludes 00H Programming
Prior to Erasure
Chip Program Time
124
2
12 5 Sec Excludes System-Level Overhead
Erase Program Cycles 1 5 1 000 100 000
Cycles
NOTES
1 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples taken from production lots Data taken at
T e 25 C VPP e 12 0V VCC e 5 0V
2 Minimum byte programming time excluding system overhead is 16 msec (10 msec program a 6 msec write recovery)
while maximum is 400 msec byte (16 msec x 25 loops allowed by algorithm) Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte
3 Excludes 00H programming prior to erasure
4 Excludes system-level overhead
5 Refer to RR-60 ‘‘ETOX Flash Memory Reliability Data Summary’’ for typical cycling data and failure rate calculations
6 Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at
T e b40 C 1 000 cycles VPP e 11 4V VCC e 4 5V
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