TTSI1K16T 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

Agere -> LSI Corporation 

Preliminary Data Sheet

February 1999

TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

List of Figures

Figures

Page

Figure 1. Block Diagram of the TTSI1K16T .............................................................................................................6

Figure 2. 144-Pin TQFP Pin Assignment (Top View)...............................................................................................7

Figure 3. A Typical TSI Application ........................................................................................................................13

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs ..........................................................................................15

Figure 5. Asynchronous Read................................................................................................................................16

Figure 6. Asynchronous Write................................................................................................................................16

Figure 7. Synchronous Read .................................................................................................................................17

Figure 8. Synchronous Write..................................................................................................................................17

Figure 9. Mixed-Highway Data Rates ....................................................................................................................19

Figure 10. Virtual and Physical Frames .................................................................................................................20

Figure 11. Synchronization to FSYNC ...................................................................................................................21

Figure 12. Highway Offsets ....................................................................................................................................22

Figure 13. Mixed Low-Latency and Frame-Integrity Modes ...................................................................................26

Figure 14. Block Diagram of the TTSI1K16T's Boundary-Scan Test Logic ...........................................................29

Figure 15. BS TAP Controller State Diagram.........................................................................................................30

Figure 16. Asynchronous Read Cycle Timing Using DT Handshake.....................................................................55

Figure 17. Asynchronous Write Cycle Timing Using DT Handshake .....................................................................55

Figure 18. Asynchronous Read Cycle Timing Using Only CS ...............................................................................56

Figure 19. Asynchronous Write Cycle Timing Using Only CS ...............................................................................56

Figure 20. Synchronous Read Cycle Timing..........................................................................................................57

Figure 21. Synchronous Write Cycle Timing ..........................................................................................................57

Figure 22. TDM Highway Timing............................................................................................................................59

Figure 23. JTAG Interface Timing ..........................................................................................................................60

Lucent Technologies Inc.

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