TTSI1K16T3TL 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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TTSI1K16T3TL

1024-Channel, 16-Highway Time-Slot Interchanger

Agere -> LSI Corporation 

TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

Preliminary Data Sheet

February 1999

Functional Description (continued)

The device capabilities include several test features for board and device diagnostics.

s Test-pattern checking on input time slots (PRBS, QRSS, or a fixed byte).

s Test-pattern generation on output time slots (PRBS, QRSS, or a fixed byte).

s JTAG on all I/O.

s Software-controlled BIST of data store and connection store memory.

s TEST pin for isolating the TTSI1K16T during board test.

The microprocessor interface supports two modes of operation, synchronous and asynchronous. These modes are

selected based on the MM input pin. Both modes provide an 8-bit demultiplexed address and data bus. Fifteen

address pins allow direct access to the 32 Kbyte address space. This interface provides direct access to the control

registers and data store and connection store memories.

The TTSI1K16T is fabricated using a low-power, high-density, CMOS process that nominally operates at 3.3 V with

TTL switching thresholds and 5 V tolerance on the inputs and outputs. A basic block diagram of the architecture is

shown in Figure 1.

RXD0

RXD1

RXD2

RXD3

RXD14

RXD15

FSYNC

CK

CKSPD0

CKSPD1

CKSPD2

RECEIVE

HIGHWAYS

TDM

DATA

DATA

STORE

TDM

DATA

TRANSMIT

HIGHWAYS

PLL

AND

CK

LOGIC

DATA STORE

ADDRESS

CONNECTION

STORE

JTAG

TXD0

TXOE0

TXD1

TXOE1

TXD15

TXOE15

TCK

TDI

TMS

TRST

TDO

HOST ADDRESS/DATA BUS

MM

MICROPROCESSOR INTERFACE

RESET

TEST

INT

A[14—0] D[7—0] CS AS DS R/W

PCLK DT

5-5780(F).c

Figure 1. Block Diagram of the TTSI1K16T

6

Lucent Technologies Inc.

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