CAT24AA16(2018) 데이터 시트보기 (PDF) - ON Semiconductor
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CAT24AA16 Datasheet PDF : 11 Pages
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CAT24AA16
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. REABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
NEND (Note 3)
Endurance
1,000,000
Program/Erase Cycles
TDR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode @ 25°C
Table 3. DC OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
ICCR
ICCW
ISB
IL
VIL
VIH
VOL1
VOL2
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Read, fSCL = 400 kHz
Write, fSCL = 400 kHz
All I/O Pins at GND or VCC
Pin at GND or VCC
VCC w 2.5 V, IOL = 3.0 mA
VCC < 2.5 V, IOL = 1.0 mA
−0.5
VCC x 0.7
0.5
1
1
1
VCC x 0.3
VCC + 0.5
0.4
0.2
Units
mA
mA
mA
mA
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 4)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 4)
Input Capacitance (Other Pins)
VIN = 0 V
6
pF
IWP (Note 5)
WP Input Current
VIN < 0.5 x VCC, VCC = 5.5 V
200
mA
VIN < 0.5 x VCC, VCC = 3.3 V
150
VIN < 0.5 x VCC, VCC = 1.8 V
100
VIN > 0.5 x VCC
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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