CAT24C256LI-G 데이터 시트보기 (PDF) - ON Semiconductor
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CAT24C256LI-G Datasheet PDF : 18 Pages
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CAT24C256
Table 5. D.C. OPERATING CHARACTERISTICS − New Product (Rev E) (Note 7)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
ICCR
ICCW
ISB
IL
VIL1
VIL2
VIH1
VIH2
VOL1
VOL2
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Read, fSCL = 400 kHz/1 MHz
All I/O Pins at GND or VCC
Pin at GND or VCC
2.5 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.5 V
VCC ≥ 2.5 V, IOL = 3.0 mA
VCC < 2.5 V, IOL = 1.0 mA
TA = −40°C to +85°C
TA = −40°C to +125°C
TA = −40°C to +85°C
TA = −40°C to +125°C
−0.5
−0.5
0.7 VCC
0.75 VCC
1
3
2
5
1
2
0.3 VCC
0.25 VCC
VCC + 0.5
VCC + 0.5
0.4
0.2
Units
mA
mA
mA
mA
V
V
V
V
V
V
Table 6. PIN IMPEDANCE CHARACTERISTICS − New Product (Rev E) (Note 7)
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 8)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 8)
Input Capacitance (other pins)
VIN = 0 V
6
pF
IWP, IA (Note 9)
WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.3 V
75
mA
50
VIN < VIH, VCC = 1.8 V
25
VIN > VIH
2
7. The new product Rev E is identified by letter “E” or a dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
9. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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