MTV512MV 데이터 시트보기 (PDF) - Myson Century Inc
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MTV512MV Datasheet PDF : 26 Pages
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MTV512M
Preliminary
FUNCTIONAL DESCRIPTIONS
8051 CPU Core
The CPU core of MTV512M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and a serial UART interface. The CPU core
fetches its program code from the 64K bytes Flash memory in MTV512M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. When the operating X’tal is 12MHz, Once the bit is set,
the CPU runs as if a 24MHz X’tal is applied on MTV512M, but the peripherals (IIC, DDC, Etimer, ADC, DAC)
still run at the original frequency.
Note: All registers listed in this document reside in 8051’s external RAM area (XFR). For internal RAM
memory map, please refer to 8051 spec.
Memory Allocation
i) Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
ii) Internal RAM
There are total 256 bytes internal RAM in MTV512M, the same as standard 8052.
iii) External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h – FFFh. These registers are
used for special functions. Programs can use "MOVX" instruction to access these registers.
iv) Auxiliary RAM (AUXRAM)
There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 8FFh. Programs can
use "MOVX" instruction to access the AUXRAM.
v) Dual Port RAM (DDCRAM)
There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can use
"MOVX" instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC0x
EEPROM is connected onto the interface. Address from E00h to E7Fh is for external DDC host1 to access the
DDC data. Address from E80h to EFFh is for external DDC host2.
FFh Internal RAM
SFR
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
80h
7Fh Internal RAM
Accessible by
direct addressing
Accessible by
direct and indirect
addressing
00h
FFFh
XFR
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
F00h
EFFh
E80h
E7Fh
8FFh
E00h
8FFh
800h
DDCRAM2
Accessible by
indirect external
RAM addressing
(Using MOVX
Instruction)
DDCRAM1
Accessible by
indirect external
RAM addressing
(Using MOVX
Instruction)
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
Instruction)
page 7 of 7
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