CY2DL1510AZI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY2DL1510AZI Datasheet PDF : 15 Pages
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CY2DL1510
1:10 Differential LVDS Fanout Buffer
Features
■ Low-voltage differential signal (LVDS) input with on-chip 100-Ω
input termination resistor
■ Ten differential LVDS outputs
■ 40-ps maximum output-to-output skew
■ 600-ps maximum propagation delay
■ 0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■ Up to 1.5-GHz operation
■ Synchronous clock enable function
■ 32-pin thin quad flat pack (TQFP) package
■ 2.5-V or 3.3-V operating voltage[1]
■ Commercial and industrial operating temperature range
Functional Description
The CY2DL1510 is an ultra-low noise, low-skew,
low-propagation delay 1:10 differential LVDS fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The on-chip 100-Ω input termination
resistor reduces board component count, while the synchronous
clock enable function ensures glitch-free output transitions
during enable and disable periods. The device has a fully
differential internal architecture that is optimized to achieve
low-additive jitter and low-skew at operating frequencies of up to
1.5 GHz.
Logic Block Diagram
Q0
Q0#
VDD
VSS
IN
100
IN#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Q4
Q4#
CLK_EN
VDD
100k
Q
D
VBB
Q5
Q5#
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54863 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 25, 2011
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