CY2DL1510AZI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY2DL1510AZI

1:10 Differential LVDS Fanout Buffer

Cypress Semiconductor 

Pinouts

CY2DL1510

Figure 1. Pin Diagram - CY2DL1510

VDD

Q2#

Q2

Q1#

Q1

Q0#

Q0

VDD

24 23 22 21 20 19 18 17

25

16

26

15

27

14

28

CY2DL1510

13

29

12

30

11

31

10

32

9

1 23 456 7

8

VDD

Q7

Q7#

Q8

Q8#

Q9

Q9#

VDD

Table 1. Pin Definitions

Pin No.

1, 9, 16, 25, 32

2

Pin Name

VDD

CLK_EN

Pin Type

Power

Input

3, 4

NC

5

VBB

6

IN

7

IN#

8

VSS

10,12,14,17,19,21, Q(0:9)#

23,26,28,30

11,13,15,18,20,22, Q(0:9)

24,27,29,31

Output

Input

Input

Power

Output

Output

Description

Power supply

Synchronous clock enable. Low-voltage complementary metal oxide

semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).

When CLK_EN = Low, Q(0:9) outputs are held low and Q(0:9)# outputs are

held high

No connection

LVDS reference voltage output

LVDS input clock

LVDS complementary input clock

Ground

LVDS complementary output clocks

LVDS output clocks

Document Number: 001-54863 Rev. *H

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