CY2DL1510AZI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY2DL1510AZI Datasheet PDF : 15 Pages
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CY2DL1510
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min Max Unit
IDD
Operating supply current
All LVDS outputs terminated with 100 Ω
load[3, 4]
–
125 mA
VIH1
Input high Voltage, LVDS input clocks,
IN and IN#
– VDD + 0.3 V
VIL1
Input low voltage, LVDS input clocks,
IN and IN#
–0.3
–
V
VIH2
VIL2
VIH3
VIL3
VID[5]
VICM
IIH
IIL
VPP
ΔVOCM
VBB
RTERM
Input high voltage, CLK_EN
Input low voltage, CLK_EN
Input high voltage, CLK_EN
Input low voltage, CLK_EN
Input differential amplitude
VDD = 3.3 V
VDD = 3.3 V
VDD = 2.5 V
VDD = 2.5 V
See Figure 3 on page 7
2.0 VDD + 0.3 V
–0.3
0.8
V
1.7 VDD + 0.3 V
–0.3
0.7
V
0.4
0.8
V
Input common mode voltage
Input high current, All inputs
Input low current, All inputs
See Figure 3 on page 7
Input = VDD[6]
Input = VSS[6]
0.5 VDD – 0.2 V
–
150 μA
–150
–
μA
LVDS differential output voltage peak to
peak, single-ended
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between
Q
and
Q#
pairs[3,
7]
250
470 mV
Change in VOCM between complementary
output states
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between
Q
and
Q#
pairs[3,
7]
–
50
mV
Output reference voltage
0 to 150 μA output current
1.125 1.375 V
On-chip differential input termination
resistor
80
120
Ω
RP
Internal pull-up resistance,
LVCMOS logic input
CLK_EN pin
60
140 kΩ
CIN
Input capacitance
Measured at 10 MHz per pin
–
3
pF
Notes
3. Refer to Figure 2 on page 7.
4. IDD includes current that is dissipated externally in the output termination resistors.
5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to Figure 4 on page 7.
Document Number: 001-54863 Rev. *H
Page 5 of 15
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