SST39VF040 데이터 시트보기 (PDF) - Microchip Technology

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SST39VF040

IC FLASH 2MBIT 70NS 32PLCC

Microchip Technology 

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Data# Polling (DQ7)

When the SST39LF010/020/040 and SST39VF010/020/040 are in the internal Program operation, any

attempt to read DQ7 will produce the complement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately

following completion of an internal Write operation, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs.

During internal Erase operation, any attempt to read DQ7 will produce a “0”. Once the internal Erase

operation is completed, DQ7 will produce a “1”. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after

the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure

16 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce

alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation

is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is

valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle

Bit timing diagram and Figure 16 for a flowchart.

Data Protection

The SST39LF010/020/040 and SST39VF010/020/040 provide both hardware and software features to

protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

©2012 Silicon Storage Technology, Inc.

8

DS25023B

06/13

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