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74VHCT125BQ

Quad buffer/line driver; 3-state

NXP Semiconductors. 

74VHC125; 74VHCT125

Quad buffer/line driver; 3-state

Rev. 02 — 13 October 2009

Product data sheet

1. General description

The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin

compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with

JEDEC standard JESD7-A.

The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state

outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH

at nOE causes the outputs to assume a high-impedance OFF-state.

The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active

LOW enable inputs.

2. Features

I Balanced propagation delays

I All inputs have a Schmitt-trigger action

I Inputs accepts voltages higher than VCC

I Input levels:

N The 74VHC125 operates with CMOS logic levels

N The 74VHCT125 operates with TTL logic levels

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Multiple package options

I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

74VHC125D

74VHCT125D

−40 °C to +125 °C SO14

plastic small outline package; 14 leads;

body width 3.9 mm

74VHC125PW −40 °C to +125 °C

74VHCT125PW

TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

74VHC125BQ −40 °C to +125 °C

74VHCT125BQ

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

Version

SOT108-1

SOT402-1

SOT762-1

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