74HCT109D,652 데이터 시트보기 (PDF) - NXP Semiconductors.
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74HCT109D,652 Datasheet PDF : 19 Pages
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5. Pinning information
5.1 Pinning
+&
+&7
5'
-
.
&3
6'
4
4
*1'
9&&
5'
-
.
&3
6'
4
4
DDD
Fig 4. Pin configuration for SO16
5.2 Pin description
Table 2. Pin description
Symbol
1RD, 2RD
1J, 2J
1K, 2K
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
VCC
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
+&
+&7
5'
-
.
&3
6'
4
4
*1'
9&&
5'
-
.
&3
6'
4
4
DDD
Fig 5. Pin configuration for (T)SSOP16
Description
asynchronous reset input (active LOW)
synchronous input
synchronous input
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
supply voltage
74HC_HCT109
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 August 2016
© Nexperia B.V. 2017. All rights reserved
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