74LVC109D,118 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC109D,118 Datasheet PDF : 18 Pages
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Philips Semiconductors
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
74LVC109
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS VCC (V)
MIN.
TYP. MAX. UNIT
Tamb = −40 to 125 °C
tPHL/tPLH propagation delay nCP to nQ and see Figs 6 and 8 2.7
1.5
−
nCP to nQ
3.0 to 3.6 1.0
−
tPLH
propagation delay nSD to nQ and see Figs 7 and 8 2.7
1.5
−
nRD to nQ
3.0 to 3.6 1.0
−
9.5
ns
8.5
ns
10.5 ns
9.0
ns
tPHL
propagation delay nSD to nQ and see Figs 7 and 8 2.7
1.5
−
nRD to nQ
3.0 to 3.6 1.0
−
9.0
ns
8.5
ns
tW
clock pulse width HIGH or LOW see Fig. 6
3.0 to 3.6 3.3
−
−
ns
set or reset pulse width HIGH or see Fig. 7
3.0 to 3.6 3.0
−
−
ns
LOW
trem
tsu
th
fmax
tsk(0)
removal time nSD, nRD to nCP
set-up time nJ and nK to CP
hold time nJ and nK to nCP
maximum clock pulse frequency
skew
see Fig. 7
see Fig. 6
see Fig. 6
see Fig. 6
note 3
3.0 to 3.6 3.0
−
3.0 to 3.6 2.5
−
3.0 to 3.6 2.0
−
3.0 to 3.6 150
−
3.0 to 3.6 −
−
−
ns
−
ns
−
ns
−
MHz
1.5
ns
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
2004 Mar 18
10
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