74LVC109D,118 데이터 시트보기 (PDF) - NXP Semiconductors.

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74LVC109D,118

Dual JK flip-flop with set and reset; positive-edge trigger

NXP Semiconductors. 

Philips Semiconductors

Dual JK flip-flop with set and reset;

positive-edge trigger

PINNING

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1RD

1J

1K

1CP

1SD

1Q

1Q

GND

2Q

2Q

2SD

2CP

2K

2J

2RD

VCC

SYMBOL

DESCRIPTION

asynchronous reset input (active LOW)

synchronous input

synchronous input

clock input (LOW-to-HIGH; edge-triggered)

asynchronous set input (active LOW)

true flip-flop output

complement flip-flop output

ground (0 V)

complement flip-flop output

true flip-flop output

asynchronous set input (active LOW)

clock input (LOW-to-HIGH; edge-triggered)

synchronous input

synchronous input

asynchronous reset input (active LOW)

supply voltage

Product specification

74LVC109

handbook, halfpage

1RD 1

1J 2

1K 3

1CP 4

1SD 5

1Q 6

1Q 7

GND 8

16 VCC

15 2RD

14 2J

13 2K

10 9

12 2CP

11 2SD

10 2Q

9 2Q

MNA855

handbook, halfpage

5 11

1SD 2SD

SD

2 1J

14 2J J

1Q 6

Q

2Q 10

4 1CP CP

12

3

13

2CP

1K

2K

FF

K

Q

RD

1Q

2Q

7

9

1RD 2RD

1 15 MNA858

Fig.1 Pin configuration SO16 and (T)SSOP16.

2004 Mar 18

4

Fig.2 Logic symbol.

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