74LVC573ADB 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC573ADB
NXP Semiconductors.
74LVC573ADB Datasheet PDF : 20 Pages
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NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3. Functional table[1]
Operating modes
Input
OE
LE
Dn
Enable and read register
(transparent mode)
L
H
L
L
H
H
Latch and read register
L
L
l
L
L
h
Latch register and disable outputs
H
L
l
H
L
h
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
7. Limiting values
Internal latch Output
Qn
L
L
H
H
L
L
H
H
L
Z
H
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0
VO > VCC or VO < 0
VO = 0 V to VCC
Tamb = 40 C to +125 C
0.5
50
[1] 0.5
-
[2] 0.5
-
-
100
65
[3] -
+6.5
V
-
mA
+6.5
V
50
mA
VCC + 0.5 V
50
mA
100
mA
-
mA
+150
C
500
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LVC573A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 19 February 2013
© NXP B.V. 2013. All rights reserved.
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