74LVC86AD 데이터 시트보기 (PDF) - NXP Semiconductors.

부품명

상세내역

제조사

74LVC86AD

Quad 2-input EXCLUSIVE-OR gate

NXP Semiconductors. 

Philips Semiconductors

Quad 2-input EXCLUSIVE-OR gate

Product specification

74LVC86A

FEATURES

• 5 V tolerant inputs, for interfacing with 5 V logic

• Supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Inputs accept voltage up to 5.5 V

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC86A is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. This

feature allows the use of these devices as translators in a

mixed 3.3 and 5 V environment.

The 74LVC86A provides the 2-input EXCLUSIVE-OR

function.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.

SYMBOL

tPHL/tPLH

CI

CPD

PARAMETER

propagation delay nA, nB to nY

input capacitance

power dissipation capacitance per gate

CONDITIONS

CL = 50 pF; VCC = 3.3 V

VCC = 3.3 V; notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

TYPICAL

3.0

5.0

20

UNIT

ns

pF

pF

FUNCTION TABLE

See note 1.

INPUT

nA

nB

L

L

L

H

H

L

H

H

Note

1. H = HIGH voltage level;

L = LOW voltage level.

OUTPUT

nY

L

H

H

L

2004 Mar 04

2

Share Link: