EN80C186EA13 데이터 시트보기 (PDF) - Intel
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EN80C186EA13 Datasheet PDF : 56 Pages
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DC Specifications
8.0
DC Specifications
Table 9.
DC SPECIFICATIONS (80C186EA/80C188EA)
(
)
Symbol
Parameter
Min
Max Units
Conditions
VCC
VIL
VIH
VOL
VOH
VHYR
IIL1
Supply Voltage
45
55
V
Input Low Voltage for All Pins
Input High Voltage for All Pins
Output Low Voltage
Output High Voltage
b0 5
0 3 VCC
V
0 7 VCC VCC a 0 5 V
0 45
V IOL e 3 mA (min)
VCC b 0 5
V IOH e b2 mA (min)
Input Hysterisis on RESIN
0 30
V
Input Leakage Current (except
RD QSMD UCS LCS MCS0 PEREQ
MCS1 ERROR LOCK and TEST BUSY)
g10
mA 0V s VIN s VCC
IIL2
Input Leakage Current
b275
(RD QSMD UCS LCS MCS0 PEREQ
MCS1 ERROR LOCK and TEST BUSY
mA VIN e 0 7 VCC
(Note 1)
IOL
Output Leakage Current
g10
mA
0 45 s VOUT s VCC
(Note 2)
ICC
Supply Current Cold (RESET)
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
105
mA (Notes 3 5)
90
mA
65
mA
IID
Supply Current In Idle Mode
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
90
mA (Note 5)
70
mA
46
mA
IPD
Supply Current In Powerdown Mode
80C186EA25 80C188EA25
80C186EA20 80C188EA20
80C186EA13 80C188EA13
100
mA (Note 5)
100
mA
100
mA
COUT
CIN
Output Pin Capacitance
Input Pin Capacitance
0
15
pF TF e 1 MHz (Note 4)
0
15
pF TF e 1 MHz
NOTES:
1.RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK and TEST/BUSY have internal pull-ups that
are only activated during RESET. Loading these pins above IOL = -275 µA will cause the processor to
enter alternate modes of operation.
2.Output pins are floated using HOLD or ONCE Mode.
3.Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test
Conditions, and with the device in RESET (RESIN held low). RESET is worst case for ICC.
4.Output capacitance is the capacitive load of a floating output pin.
5.Operating conditions for 25 MHz are 0°C to +70°C, VCC = 5.0V ±10%.
26
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