EN80C186EA13 데이터 시트보기 (PDF) - Intel

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EN80C186EA13

16-Bit High-Integration Embedded Processors

Intel 

DC Specifications

8.2

PDTMR Pin Delay Calculation

The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal

clocks when exiting Powerdown. A delay is required only when using the on-chip oscillator to

allow the crystal or resonator circuit time to stabilize.

Note: The PDTMR pin function does not apply when RESIN is asserted (i.e., a device reset during

Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has

stabilized).

To calculate the value of capacitor required to provide a desired delay, use the equation:

Example 1.

440 × t = CPD (5V, 25 °C)

Where: t = desired delay in seconds

CPD = capacitive load on PDTMR in microfarads

To get a delay of 300 µs, a capacitor value of CPD = 440 × (300 × 10-6) = 0.132 µF is

required. Round up to standard (available) capacitive values.

Note:

The above equation applies to delay times greater than 10 µs and will compute the TYPICAL

capacitance needed to achieve the desired delay. A delay variance of +50% or -25% can occur due

to temperature, voltage, and device process extremes. In general, higher VCC and/or lower

temperature will decrease delay time, while lower VCC and/or higher temperature will increase

delay time.

Product Name Datasheet

29

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