EN80C186EA13 데이터 시트보기 (PDF) - Intel

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EN80C186EA13

16-Bit High-Integration Embedded Processors

Intel 

2.0

2.1

2.2

Intel® 80C186EA Core Architecture

Intel® 80C186EA Core Architecture

Bus Interface Unit

The 80C186EA core incorporates a bus controller that generates local bus control signals. In

addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle

status information and data (for write operations) information. It is also responsible for reading

data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend

a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates a control signal (DEN) when interfacing to external

transceiver chips. This capability allows the addition of transceivers for simple buffering of the

multiplexed address/data bus.

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation.

The clock generator features a crystal oscillator, a divideby- two counter, and two low-power

operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-

overtone mode crystal network. Alternatively, the oscillator circuit may be driven from an external

clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency

due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and

the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to

drive other system components. All AC timings are referenced to CLKOUT.

The following parameters are recommended when choosing a crystal:

Temperature Range:

Application Specific

ESR (Equivalent Series Resistance): 60 Ω max

C0 (Shunt Capacitance of Crystal): 7 pF max

CL (Load Capacitance):

Drive Level:

20 pF ± 2 pF

2 mW maximum

Product Name Datasheet

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