MR20H40CDC 데이터 시트보기 (PDF) - Extech Instruments Corporation.

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MR20H40CDC

NVRAM 4Mb 3.3V 512Kx8 SPI

Extech Instruments Corporation. 

MR20H40 / MR25H40

SPI COMMUNICATIONS PROTOCOL

The MR2xH40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).

For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling

edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high.

The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when

CS falls.

All memory transactions start when CS is brought low to the memory. The first byte is a command code.

Depending upon the command, subsequent bytes of address are input. Data is either input or output.

There is only one command performed per CS active period. CS must go inactive before another command

can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate

each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial

or aborted accesses.

Command Codes

Instruction

WREN

WRDI

RDSR

WRSR

READ

WRITE

SLEEP

WAKE

Description

Write Enable

Write Disable

Read Status Register

Write Status Register

Read Data Bytes

Write Data Bytes

Enter Sleep Mode

Exit Sleep Mode

Table 2 – Command Codes

Binary Code Hex Code

0000 0110

06h

0000 0100

04h

0000 0101

05h

0000 0001

01h

0000 0011

03h

0000 0010

02h

1011 1001

B9h

1010 1011

ABh

Address Bytes

0

0

0

0

3

3

0

0

Data Bytes

0

0

1

1

1 to ∞

1 to ∞

0

0

Status Register, Memory Protection and Block Write Protection

The status register consists of the 8 bits listed in Table 3. As seen in Table 4, the Status Register Write Disable

bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware

memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected as described

in Table 5. The fast writing speed of the MR2xH40 does not require write status bits. The state of bits 6,5,4,

and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set

from the factory in the “0” state.

Table 3 – Status Register Bit Assignments

Bit 7

SRWD

Bit 6

Bit 5

Bit 4

Don’t Care Don’t Care Don’t Care

Bit 3

BP1

Bit 2

BP0

Bit 1

WEL

Bit 0

Don’t Care

Copyright © Everspin Technologies 2014

7

MR20H40 / MR25H40 Revision 11, 8/2014

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