ADM8693ANZ 데이터 시트보기 (PDF) - Analog Devices
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ADM8693ANZ Datasheet PDF : 20 Pages
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ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
The ADM8691/ADM8693/ADM8695 allow these times to be
adjusted, as shown in Table 5. Figure 17, Figure 18, Figure 19,
and Figure 20 show the various oscillator configurations that
can be used to adjust the reset pulse width and watchdog
timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; and
with it connected low, the 100 ms timeout period is selected. In
either case, the timeout period is 1.6 seconds immediately after
a reset. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, the 100 ms watchdog period becomes
effective after the first transition of WDI. The software should
be written such that the input/output port driving WDI is left in
its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period of 70 ms.
WATCHDOG OUTPUT (WDO)
The Watchdog Output WDO (ADM8691/ADM8693/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input. WDO is also set high when VCC goes
below the reset threshold.
CLOCK
0 TO 500kHz
8
OSC SEL
ADM8691/
ADM8693/
ADM8695
7
OSC IN
Figure 17. External Clock Source
COSC
8
OSC SEL
ADM8691/
ADM8693/
ADM8695
7 OSC IN
Figure 18. External Capacitor
8
NC
OSC SEL
ADM8691/
ADM8693/
ADM8695
NC
7
OSC IN
Figure 19. Internal Oscillator (1.6 Second Watchdog)
8
NC
OSC SEL
ADM8691/
ADM8693/
ADM8695
7
OSC IN
Figure 20. Internal Oscillator (100 ms Watchdog)
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8693/ADM8695)
The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry that ensures the integrity of data
in memory by preventing write operations when VCC is at an
invalid level. There are two additional pins (CEIN and CEOUT)
that can be used to control the chip enable or write inputs of
CMOS RAM. When VCC is present, CEOUT is a buffered replica
of CEIN, with a 3 ns propagation delay. When VCC falls below the
reset voltage threshold or VBATT, an internal gate forces CEOUT
high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed up CMOS RAM. This ensures the integrity of the data in
memory by preventing write operations when VCC is at an
invalid level. Similar protection of EEPROMs can be achieved
using the CEOUT to drive the store or write inputs.
ADM8691
ADM8693
ADM8695
CEIN
CEOUT
VCC LOW = 0
VCC OK = 1
Figure 21. Chip Enable Gating
VCC
V2
V1
V2
V1
RESET
t1
t1
LOW LINE
CEIN
CEOUT
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 22. Chip Enable Timing
Rev. B | Page 12 of 20
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