AD9731(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD9731 Datasheet PDF : 11 Pages
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AD9731
1
–10
–20
ENCODE = 125MHz
AOUT1 = 800kHz
–30
AOUT2 = 900kHz
SPAN = 2MHz
1AP
–40
–50
–60
1
–70
–80
–90
–100
0Hz
START
200kHz
2MHz
STOP
Figure 14. Wideband Intermodulation Distortion
F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 2 MHz
1
–10
–20
–30
–40
ENCODE = 125MHz
AOUT1 = 800kHz
AOUT2 = 900kHz
SPAN = 62.5MHz
1AP
–50
–60
PRN
–70
1
–80
–90
–100
0Hz
START
6.25MHz
62.5MHz
STOP
Figure 15. Wideband Intermodulation Distortion F1 =
800 kHz; F2 = 900 kHz; 125 MHz Clock; Span = 62.5 MHz
THEORY AND APPLICATIONS
The AD9731 high speed digital-to-analog converter utilizes
most significant bit decoding and segmentation techniques to
reduce glitch impulse and deliver high dynamic performance
on lower power consumption than previous bipolar DAC
technologies.
The design is based on four main subsections: the decoder/
driver circuits, the edge-triggered data register, the switch net-
work and the control amplifier. An internal bandgap reference is
included to allow operation of the device with minimum exter-
nal support components.
Digital Inputs/Timing
The AD9731 has TTL/high speed CMOS-compatible single-
ended inputs for data inputs and clock. The switching threshold
is +1.5 V.
In the decoder/driver section, the three MSBs are decoded to
seven “thermometer code” lines. An equalizing delay is included
for the seven least significant bits and the clock signals. This
delay minimizes data skew and data setup and hold times at the
register inputs.
The on-board register is rising-edge triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data setup and hold times as shown in the
timing diagram. Although the AD9731 is designed to provide
isolation of the digital inputs to the analog output, some cou-
pling of digital transitions is inevitable. Digital feedthrough can
be minimized by forming a low-pass filter at the digital input by
using a resistor in series with the capacitance of each digital
input. This common high speed DAC application technique has
the effect of isolating digital input noise from the analog output.
References
The internal bandgap reference, control amplifier and reference
input are pinned out to provide maximum user flexibility in
configuring the reference circuitry for the AD9731. When using
the internal reference, REF OUT (Pin 25) should be connected
to CONTROL AMP IN (Pin 26). CONTROL AMP OUT (Pin
24) should be connected to REF IN (Pin 23). A 0.1 µF ceramic
capacitor connected from Pin 23 to Analog –VS (Pin 22) im-
proves settling time by decoupling switching noise from the
current sink baseline. A reference current cell provides feedback
to the control amplifier by sinking current through RSET (Pin 17).
Full-scale current is determined by CONTROL AMP IN and
RSET according to the following equation:
IOUT (FS) = 32(CONTROL AMP IN/RSET)
The internal reference is nominally –1.25 V with a tolerance of
± 8% and typical drift over temperature of 100 ppm/°C. If
greater accuracy or temperature stability is required, an external
reference can be used. The AD589 reference features 10 ppm/°C
drift over the 0°C to +70°C temperature range.
Two modes of multiplying operation are possible with the
AD9731. Signals with bandwidths up to 2.5 MHz and input
swings from –0.6 V to –1.2 V can be applied to the CONTROL
AMP IN pin as shown in Figure 16. Because the control ampli-
fier is internally compensated, the 0.1 µF capacitor discussed
above can be reduced to maximize the multiplying bandwidth.
However, it should be noted that output settling time, for
changes in the digital word, will be degraded.
RSET
AD9731
RSET
–0.6 TO –1.2V
2.5MHz TYPICAL
CONTROL
AMP IN
RT
CONTROL
AMP OUT
0.1F
REFERENCE IN
ANALOG –VS
Figure 16. Low Frequency Multiplying Circuit
–8–
REV. A
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