ALD500 데이터 시트보기 (PDF) - Advanced Linear Devices
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ALD500 Datasheet PDF : 11 Pages
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DC ELECTRICAL CHARACTERISTICS
TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47µf
Parameter
Supply Current
500AU
500A
500
Symbol Min Typ Max Min Typ Max Min Typ Max
Unit Test Conditions
IS
0.6 1.0
0.6 1.0
0.6 1.0 mA
V+ = 5V , A =1,B=1
Power Dissipation
PD
10
10
10
mW
VSUPPLY = ±5V
Positive Supply Range V+S
4.5
5.5 4.5
5.5
4.5
5.5 V
Note 4
Negative Supply Range V-S
-4.5
-5.5 -4.5
-5.5 -4.5
-5.5 V
Note 4
Comparator Logic 1,
Output High
Comparator Logic 0,
Output Low
Logic 1, Input High
Voltage
Logic 0, Input Low
Voltage
Logic Input Current
Comparator Delay
VOH
4
4
4
V
ISOURCE = 400µA
VOL
0.4
0.4
0.4 V
ISINK = 1.1mA
VIH
3.5
3.5
3.5
V
VIL
1
1
1V
IL
0.01
tD
1
0.01
0.01
µA
1
1
µsec Note 5
NOTES:
1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., VINT ~= 4V, VIN = 2.0V Full Scale
Resolution = VINT /integrate time/clock period
2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.
3. Rollover Error also depends on CINT, CREF, CAZ characteristics.
4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V.
5. Recommended selection of clock periods of one of the following:
t clk = 0.27µsec, 0.54µsec, or 1.09µsec
which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
Figure 3. ALD500 TIMING DIAGRAM
1 Conversion Cycle
1.8432 MHz Clock
A INPUT
B INPUT
123,093
Clock Pulses
0.5416 µs
66.667 msec.
123,093
Clock Pulses
66.667 msec.
COUT
Positive Input Signal
NOT VALID
COUT
Negative Input Signal
NOT VALID
Auto Zero
Phase
Input Signal
Integration
Phase
START
CONVERSION
CYCLE
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed number
of clock pulses
by design.
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
Reference
Voltage
Deintegration
Phase
Variable
number of
clock pulses.
At VIN MAX,
max. number of
clock pulses
=~ 246,185
Integrator Zero
Phase
Auto Zero
Phase
Fixed period of
approx.1 msec.
Stop counter upon
detection of comparator
output going from high
to low state.
REPEAT
CONVERSION
CYCLE
START INTEGRATOR ZERO CYCLE
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
5
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