42568WP 데이터 시트보기 (PDF) - STMicroelectronics

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42568WP

256 Kbit Serial I2C Bus EEPROM / 4256BWP / SOP8

STMicroelectronics 

Device operation

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF

4.1

Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in

the high state. A Start condition must precede any data transfer instruction. The device

continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock

(SCL) for a Start condition.

4.2

Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and

driven high. A Stop condition terminates communication between the device and the bus

master. A Read instruction that is followed by NoAck can be followed by a Stop condition to

force the device into the Standby mode.

A Stop condition at the end of a Write instruction triggers the internal Write cycle.

4.3

Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock

(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge

of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock

(SCL) is driven low.

4.4

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,

whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits

of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to

acknowledge the receipt of the eight data bits.

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DocID6757 Rev 32

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