42568WP 데이터 시트보기 (PDF) - STMicroelectronics

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42568WP

256 Kbit Serial I2C Bus EEPROM / 4256BWP / SOP8

STMicroelectronics 

Instructions

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF

5.2.1

5.2.2

5.2.3

Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 10) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the RW bit set to 1. The device

acknowledges this, and outputs the contents of the addressed byte. The bus master must

not acknowledge the byte, and terminates the transfer with a Stop condition.

Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only

sends a device select code with the R/W bit set to 1. The device acknowledges this, and

outputs the byte addressed by the internal address counter. The counter is then

incremented. The bus master terminates the transfer with a Stop condition, as shown in

Figure 10, without acknowledging the byte.

Note that the address counter value is defined by instructions accessing either the memory

or the Identification page. When accessing the Identification page, the address counter

value is loaded with the byte location in the Identification page, therefore the next Current

Address Read in the memory uses this new address counter value. When accessing the

memory, it is safer to always use the Random Address Read instruction (this instruction

loads the address counter with the byte location to read in the memory, see Section 5.2.1)

instead of the Current Address Read instruction.

Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The

bus master does acknowledge the data byte output, and sends additional clock pulses so

that the device continues to output the next byte in sequence. To terminate the stream of

bytes, the bus master must not acknowledge the last byte, and must generate a Stop

condition, as shown in Figure 10.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output. After the last memory address, the

address counter “rolls-over”, and the device continues to output data from memory address

00h.

5.3

Read Identification Page (M24256-D only)

The Identification Page (64 bytes) is an additional page which can be written and (later)

permanently locked in Read-only mode.

The Identification Page can be read by issuing an Read Identification Page instruction. This

instruction uses the same protocol and format as the Random Address Read (from memory

array) with device type identifier defined as 1011b. The MSB address bits A15/A6 are don't

care, the LSB address bits A5/A0 define the byte address inside the Identification Page. The

number of bytes to read in the ID page must not exceed the page boundary (e.g.: when

reading the Identification Page from location 10d, the number of bytes should be less than

or equal to 54, as the ID page boundary is 64 bytes).

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