UPD16655N-XXX 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD16655N-XXX

240-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µ PD16655

3. PIN FUNCTIONS

SYMBOL

O1 to O240

PIN NAME

Driver Output

STVR

STVL

Start Pulse Input/Output

R,/L

Shift Direction Select Input

CLK

Shift Clock Input

OE

Output Enable Input

VDD1

Logic Positive Power Supply

VDD2

Driver Positive Power Supply

VCC

Reference Positive Power

Supply

VSS

Reference Negative Power

Supply

VEE1

Logic Negative Power Supply

VEE2

Driver Negative Power Supply

I/O

VSS/VCC or

VDD1/VEE1 (input)

VDD1/VEE1 (output)

VSS/VCC or

VDD1/VEE1

VSS/VCC

VSS/VCC

DESCRIPTION

These pins output scan signals that drive the vertical

direction (gate lines) of a TFT-LCD. The output signals

change in synchronization with the rising edge of shift

clock CLK. The driver output amplitude is VDD2 - VEE2.

This is the input of the internal shift register. The input

date is read at the rising edge of shift clock CLK, and

scan signals are output from the O1 through O120 pins.

The input level is a VCC/VSS or VDD1 - VEE1 level.

This pin outputs a start pulse to the µ PD16655 at the

next stage when two or more µ PD16655s are connected

in cascade.

The pulse is output at the falling edge of the 240th clock

of shift clock CLK, and is cleared at the falling edge of the

241st clock.

R,/L = “H” (right shift): STVR → O1 → O240 → STVL

R,/L = “L” (left shift): STVL → O240 → O1 → STVR

This pin inputs a shift clock to the internal shift register.

The shift operation is performed in synchronization with

the rising edge of this input.

When this pin goes “H”, the driver output is fixed to “L”.

The shift register is not cleared, however. The internal

logic operates even when OE = “H”. OE is in

asynchronization with the clock.

10 V to 25 V

10 V to 25 V

3.0 to 5.5 V Reference voltage to level shifter LS.

Connect this pin to the ground of the system.

–21 V to –3 V

–21 V to VDD2 – 15 V

Cautions 1. To prevent latch up, turn on power to VCC, VEE1-VEE2, VDD1-VDD2, and logic input in this order. Turn

off power in the reverse order. These power up/down sequence must be observed also during

transition period.

2. Insert a capacitor of about 0.1 µ F between each power line, as shown below, to secure

noise margin such as VIH and VIL, because the internal logic operates on a high voltage

level. (VDD = VDD1 = VDD2)

VDD

VCC

0.1 F

0.1 F

VSS

0.1 F

VEE

4

Data Sheet S11950EJ2V0DS00

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