UPD16655 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD16655

240-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µ PD16655

3. In an application where the VEE power supply is not shifted, short-circuit VEE2 (driver power) and VEE1

(logic power) outside the TCP. Fix unused pins to the VEE level.

4. The level shift range of VEE2 must be VEE1 ≤ VEE2 ≤ VDD – 15 V. Note that, in this case, the guaranteed

values of the output ON resistance and output fall time slightly change. (VDD = VDD1 = VDD2)

5. TIMING CHART

1

2

3

CLK

239

240

241

242

STVR

(STVL)

O1

O2

O3

O239

O240

STVL

(STVR)

O1 of

next stage

O2 of

next stage

Caution Do not use a sequence in which the outputs change all at once because such a sequence may

cause malfunctioning.

Data Sheet S11950EJ2V0DS00

5

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