AS7C1025C-15JIN 데이터 시트보기 (PDF) - Alliance Semiconductor
부품명
상세내역
제조사
AS7C1025C-15JIN Datasheet PDF : 10 Pages
| |||
AS7C1025C
®
Functional description
The AS7C1025C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized
as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 15 ns with output enable access times (tOE) of 6 ns are ideal for high-
performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory
systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025C is packaged in
common industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
Vt1
Vt2
PD
Tstg
Tbias
IOUT
–0.50
–0.50
–
–55
–55
–
+7.0
V
VCC + 0.5
V
1.25
W
+125
oC
+125
oC
50
mA
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
H
X
X
L
H
H
L
H
L
L
L
X
Key: X = don’t care, L = low, H = high.
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
12/5/06, v. 1.0
Alliance Memory
P. 2 of 9
Share Link: 