AT88SA10HS(2009) 데이터 시트보기 (PDF) - Atmel Corporation

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AT88SA10HS
(Rev.:2009)

CryptoAuthentication Host Security Chip

Atmel Corporation 

3.2.

IO Blocks

Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the

following way:

Byte

Number

Name

0

Count

1 to (N-2) Packet

N-1, N Checksum

Meaning

Number of bytes to be transferred to the chip in the block, including count, packet and

checksum, so this byte should always have a value of (N+1). The maximum size block is

39 and the minimum size block is 4. Values outside this range will cause unpredictable

operation.

Command, parameters and data, or response. Refer to Section 3.1.2 & Section 4 for more

details.

CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the

initial register value should be 0 and after the last bit of the count and packet have been

transmitted the internal CRC register should have a value that matches that in the block.

The first byte transmitted (N-1) is the least significant byte of the CRC value so the last

byte of the block is the most significant byte of the CRC.

3.3.

IO Flow

The general IO flow for the commands is as follows:

1. System sends Wake token.

2. System sends Transmit flag.

3. Receive 0x11 value from the AT88SA10HS to verify proper wakeup synchronization.

4. System sends Command flag.

5. System sends complete command block.

6. System waits t PARSE for the AT88SA10HS to check for command formation errors.

7. System sends Transmit flag. If command format is OK, the AT88SA10HS ignores this flag because the

computation engine is busy. If there was an error, the AT88SA10HS responds with an error code.

8. System waits t EXEC, Refer to Section 3.1.1.

9. System sends Transmit flag.

10. Receive output block from the AT88SA10HS, system checks CRC.

11. If CRC from the AT88SA10HS is incorrect, indication transmission error, system resends Transmit flag.

12. System sends sleep flag to the AT88SA10HS.

Where the command in question has a short execution delay the system should omit steps 6, 7 & 8 and replace this

with a wait of duration t PARSE + t EXEC.

3.4.

Synchronization

Because the communications protocol is half duplex, there is the possibility that the system and the AT88SA10HS will

fall out of synchronization with each other. In order to speed recovery, the AT88SA10HS implements a timeout that

forces the AT88SA10HS to sleep.

10 AT88SA10HS Host Authentication Chip [Preliminary]

8595B–SMEM–09/09

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