LC72121V-D-MPB-E 데이터 시트보기 (PDF) - ON Semiconductor
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LC72121V-D-MPB-E Datasheet PDF : 23 Pages
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LC72121, 72121M, 72121V
Continued from preceding page.
No. Control block/data
Function
9
Clock time base
TBC
• Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the
BO1 pin. (The BO1 data will be ignored.)
• Forcibly controls the charge pump output.
DLC Charge pump output
Charge pump
10
control data
0
Normal operation
1
Forced to low
DLC
* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,
applications can get out of the deadlocked state by setting the charge pump output to low and setting
Vtune to VCC. (Deadlock clear circuit)
IF counter control • This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in
11
data
which the sensitivity is reduced by about 10 to 30 mV rms.
IFS
* See the “IF Counter Operation” section for details.
• Test data
Test data
12
TEST0 to 2
TEST0
TEST1
TEST2
All these bits must be set to 0.
All these bits are set to 0 after a power on reset.
13
DNC
• This bit must be set to 0.
Related data
BO1
Structure of the DO Output Data (serial data output)
• OUT mode
DO Output Data
No. Control block/data
Function
• Data latched from the I/O port IO1 or IO2 pin states.
I/O port data
• These bits reflect the pin states regardless of the I/O port mode (input or output).
1
The data is latched at the point the circuit enters data output mode (OUT mode).
12, I1
I1 ← The IO1 pin state H : 1
I2 ← The IO2 pin state L : 0
PLL unlocked state • Indicates the state of the unlocked state detection circuit.
2
data
UL ← 0: When the PLL is unlocked.
UL
UL ← 1: When the PLL is locked or in the detection disabled mode.
IF counter binary • Indicates the value of the IF counter (20-bit binary counter).
3
data
C19 ← MSB of the binary counter
C19 to C0
C0 ← LSB of the binary counter
Related data
IOC1
IOC2
UL0
UL1
CTE
GT0
GT1
No. 5815-11/23
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