LH28F016SC-L 데이터 시트보기 (PDF) - Sharp Electronics

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LH28F016SC-L

16 M-bit (2 MB x 8) SmartVoltage Flash Memories

Sharp Electronics 

software to suspend a block erase to read/write

data from/to blocks other than that which is

suspended. Byte write suspend allows system

software to suspend a byte write to read data from

any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer

may choose to make the VPP power supply

switchable (available only when memory block

erases, byte writes, or lock-bit configurations are

required) or hardwired to VPPH1/2/3. The device

accommodates either design practice and

encourages optimization of the processor-memory

interface.

When VPP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, byte

write, or lock-bit configuration command sequences,

provides protection from unwanted operations even

when high voltage is applied to VPP. All write

functions are disabled when VCC is below the write

lockout voltage VLKO or when RP# is at VIL. The

device’s block locking capability provides additional

protection from inadvertent code or data alteration

by gating erase and byte write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier

codes, or status register independent of the VPP

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes, or

Read Status Register) to the CUI. Upon initial

device power-up or after exit from deep power-

down mode, the device automatically resets to read

array mode. Four control pins dictate the data flow

LH28F016SC-L/SCH-L

in and out of the component : CE#, OE#, WE#,

and RP#. CE# and OE# must be driven active to

obtain data at the outputs. CE# is the device

selection control, and when active enables the

selected memory device. OE# is the data output

(DQ0-DQ7) control and when active drives the

selected memory data onto the I/O bus. WE# must

be at VIH and RP# must be at VIH or VHH. Fig. 13

illustrates a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device

outputs are disabled. Output pins DQ0-DQ7 are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in

standby mode which substantially reduces device

power consumption. DQ0-DQ7 outputs are placed

in a high-impedance state independent of OE#. If

deselected during block erase, byte write, or lock-bit

configuration, the device continues functioning, and

consuming active power until the operation

completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,

places output drivers in a high-impedance state and

turns off all internal circuits. RP# must be held low

for a minimum of 100 ns. Time tPHQV is required

after return from power-down until initial memory

access outputs are valid. After this wake-up

interval, normal operation is restored. The CUI is

reset to read array mode and status register is set

to 80H.

During block erase, byte write, or lock-bit

configuration modes, RP#-low will abort the

operation. RY/BY# remains low until the reset

operation is complete. Memory contents being

altered are no longer valid; the data may be

-8-

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