LH28F016SC-L 데이터 시트보기 (PDF) - Sharp Electronics

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LH28F016SC-L

16 M-bit (2 MB x 8) SmartVoltage Flash Memories

Sharp Electronics 

partially erased or written. Time tPHWL is required

after RP# goes to logic-high (VIH) before another

command can be written.

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash

memory. Automated flash memories provide status

information when accessed during block erase, byte

write, or lock-bit configuration modes. If a CPU

reset occurs with no flash memory reset, proper

CPU initialization may not occur because the flash

memory may be providing status information

instead of array data. SHARP’s flash memories

allow proper CPU initialization following a system

reset through the use of the RP# input. In this

application, RP# is controlled by the same RESET#

signal that resets the system CPU.

LH28F016SC-L/SCH-L

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the

manufacture code, device code, block lock

configuration codes for each block, and the master

lock configuration code (see Fig. 2). Using the

manufacture and device codes, the system CPU

can automatically match the device with its proper

algorithms. The block lock and master lock

configuration codes identify locked and unlocked

blocks and master lock-bit setting.

1FFFFF

1F0004

1F0003

1F0002

1F0001

1F0000

Reserved for

Future Implementation

Block 31 Lock Configuration Code

Reserved for

Future Implementation

Block 31

(Blocks 2 through 30)

01FFFF

010004

010003

010002

010001

010000

00FFFF

000004

000003

000002

000001

000000

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Block 1

Reserved for

Future Implementation

Master Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code Block 0

Fig. 2 Device Identifier Code Memory Map

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