HEF4046B(2016) 데이터 시트보기 (PDF) - NXP Semiconductors.

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HEF4046B
(Rev.:2016)

Phase-locked loop

NXP Semiconductors. 

Nexperia

HEF4046B

Phase-locked loop

the frequency range of input signals on which the PLL will lock if it was initially out of lock.

The frequency lock range (2fL) is defined as the frequency range of input signals on which

the loop will stay locked if it was initially in lock. The capture range is smaller or equal to

the lock range.

With phase comparator 1, the range of frequencies over which the PLL can acquire lock

(capture range) depends on the low-pass filter characteristics and this range can be made

as large as the lock range. Phase comparator 1 enables the PLL system to remain in lock

in spite of high amounts of noise in the input signal. A typical behavior of this type of

phase comparator is that it may lock onto input frequencies that are close to harmonics of

the VCO center frequency. Another typical behavior is that the phase angle between the

signal and comparator input varies between 0 and 180, and is 90 at the center

frequency. Figure 3 shows the typical phase-to-output response characteristic.

Figure 4 shows the typical waveforms for a PLL with a f0 locked phase comparator 1.

9''

9''



ƒ

ƒ

ƒ

DDH

(1) Average output voltage.

Fig 3. Signal-to-comparator inputs phase difference for comparator 1

6,*B,1

&203B,1

9&2B287





3&B287

9&2B,1

9''

966

DDH

Fig 4. Typical waveforms for phase-locked loop with a f0 locked phase comparator 1

HEF4046B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 24 March 2016

© Nexperia B.V. 2017. All rights reserved

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