HEF4046B(2016) 데이터 시트보기 (PDF) - NXP Semiconductors.

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HEF4046B
(Rev.:2016)

Phase-locked loop

NXP Semiconductors. 

Nexperia

HEF4046B

Phase-locked loop

Phase comparator 2 is an edge-controlled digital memory network. It consists of four

flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers with a

common output node. When the p-type or n-type drivers are ON, they pull the output up to

VDD or down to VSS respectively. This type of phase comparator only acts on the

positive-going edges of the signals at SIG_IN and COMP_IN. Therefore, the duty factors

of these signals are not of importance.

If the signal input frequency is higher than the comparator input frequency, the p-type

output driver is maintained ON most of the time, and both the n and p-type drivers are

OFF (3-state) the remainder of the time. If the signal input frequency is lower than the

comparator input frequency, the n-type output driver is maintained ON most of the time,

and both the n and p-type drivers are OFF the remainder of the time. If the signal input

and comparator input frequencies are equal, but the signal input lags the comparator input

in phase, the n-type output driver is maintained ON for a time corresponding to the phase

difference. If the comparator input lags the signal input in phase, the p-type output driver is

maintained ON for a time corresponding to the phase difference. Subsequently, the

voltage at the capacitor of the low-pass filter connected to this phase comparator is

adjusted until the signal and comparator inputs are equal in both phase and frequency. At

this stable point, both p and n-type drivers remain OFF and thus the phase comparator

output becomes an open circuit and keeps the voltage at the capacitor of the low-pass

filter constant.

Moreover, the signal at the phase comparator pulse output (PCP_OUT) is a HIGH level,

which can be used for indicating a locked condition. Thus, for phase comparator 2, no

phase difference exists between the signal and comparator inputs over the full VCO

frequency range. Moreover, the power dissipation due to the low-pass filter is reduced

when this type of phase comparator is used, because both p and n-type output drivers are

OFF for most of the signal input cycle. It should be noted that the PLL lock range for this

type of phase comparator is equal to the capture range, independent of the low-pass filter.

With no signal present at the signal input, the VCO is adjusted to its lowest frequency for

phase comparator 2. Figure 5 shows typical waveforms for a PLL employing this type of

locked phase comparator.

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Fig 5. Typical waveforms for phase-locked loop with a locked phase comparator 2

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Rev. 6 — 24 March 2016

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