MT88L85 데이터 시트보기 (PDF) - Microsemi Corporation

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MT88L85

3 V Integrated DTMF Transceiver with Power-Down and Adaptive Micro Interface

Microsemi Corporation 

MT88L85

3 V Integrated DTMF Transceiver with

Power-Down and Adaptive Micro Interface

Data Sheet

Features

• Complete DTMF transmitter/receiver

• Low voltage operation (2.7-3.6 V)

• Adaptive micro interface enables compatibility

with Intel and Motorola processors

• DTMF transmitter/receiver power-down via

register control or power-down pin

• Adjustable guard time

• Automatic tone burst mode

• Call progress tone detection to -30 dBm

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interconnect dialers

• Pay phones

• Remote monitor/Control systems

August 2005

Ordering Information

MT88L85AE

24 Pin PDIP

MT88L85AN

24 Pin SSOP

MT88L85AP

28 Pin PLCC

MT88L85ANR 24 Pin SSOP

MT88L85AN1 24 Pin SSOP*

MT88L85AE1 24 Pin PDIP*

MT88L85ANR1 24 Pin SSOP*

*Pb Free Matte Tin

Tubes

Tubes

Tubes

Tape & Reel

Tubes

Tubes

Tape & Reel

-40°C to +85°C

Description

The MT88L85 is a monolithic DTMF transceiver with

call progress filter. It is fabricated in CMOS technology

offering low power consumption and high reliability.

The receiver section is based upon the industry

standard MT8870 DTMF receiver. The transmitter

utilizes a switched capacitor D/A converter for low

distortion, high accuracy DTMF signalling. Internal

counters provide a burst mode such that tone bursts

can be transmitted with precise timing. A call progress

filter can be selected allowing a microprocessor to

analyze call progress tones.

TONE

∑

D/A

Converters

IN+

IN-

GS

OSC1

OSC2

Tone Burst

Gating Cct.

+

Dial

-

Tone

Filter

Oscillator

Circuit

Bias

Circuit

Control

Logic

High Group

Filter

Low Group

Filter

Control

Logic

Row and

Column

Counters

Digital

Algorithm

and Code

Converter

Steering

Logic

Transmit Data

Register

Status

Register

Control

Register

A

Control

Register

B

Receive Data

Register

Data

Bus

Buffer

Interrupt

Logic

I/O

Control

VDD VRef VSS PWDN

ESt

St/GT

Figure 1 - Functional Block Diagram

1

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved.

D0

D1

D2

D3

IRQ/CP

DS/RD

CS

R/W/WR

RS0

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