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MT88L85AN1

3 V Integrated DTMF Transceiver with Power-Down and Adaptive Micro Interface

Microsemi Corporation 

MT88L85

Data Sheet

Pin #

24 28

Name

Description

15 18

16 19

IRQ/CP

Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes

low when a valid DTMF tone burst has been transmitted or received. In call progress

mode, this pin will output a rectangular signal representative of the input signal applied at

the input op-amp. The input signal must be within the bandwidth limits of the call progress

filter. See Figure 10.

PWDN Power-down (input). Active High. Powers down the device and inhibits the oscillator.

IRQ and TONE output are high impedance. Data bus is held in tri-state. This pin has no

internal pulldown resistor. Therefore, must be tied to logic low when not used.

18 21

--

21 24

22 26

23 27

D0-D3

ESt

St/GT

Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1

(Intel). CMOS compatible.

Early Steering output. Presents a logic high once the digital algorithm has detected a

valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to

return to a logic low.

Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at

St causes the device to register the detected tone pair and update the output latch. A

voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to

reset the external steering time-constant; its state is a function of ESt and the voltage on

St.

24 28 VDD Positive power supply (3V typ.).

8,9 3,5 NC No Connection.

17

,

10,

11

16,

20,

25

Functional Description

The MT88L85 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain

setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and

pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.

The adaptive micro interface allows various microcontrollers to access the MT88L85 internal registers.

Power-Down

The MT88L85 provides enhanced power-down functionality to facilitate minimization of supply current

consumption. DTMF transmitter and receiver circuit blocks can be independently powered down via register

control. When asserted, the RxEN control bit powers down all analog and digital circuitry associated solely with the

DTMF and Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry

associated only with the DTMF transmitter in power-down mode. With the TOUT control bit asserted, the TONE

output pin is held in a high impedance (floating) state. When both power-down control bits are asserted, circuits

utilized by both the DTMF transmitter and receiver are also powered down. This power-down control disables the

crystal oscillators, and the VRef generator. In addition, the IRQ, TONE output and DATA pins are held in a high

impedance state. Finally, the whole device is put in a power-down state when the PWDN pin is asserted.

Input Configuration

The input arrangement of the MT88L85 provides a differential-input operational amplifier as well as a bias source

(VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-

amp output (GS) for gain adjustment.

3

Zarlink Semiconductor Inc.

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