DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

MT88L85AN1 데이터 시트보기 (PDF) - Microsemi Corporation

부품명
상세내역
제조사
MT88L85AN1 Datasheet PDF : 29 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MT88L85
Data Sheet
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
VDD
MT88L85
VDD
St/GT
ESt
C1
Vc
R1
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the following inequalities (see Figure 7):
tREC tDPmax + tGTPmax - tDAmin
t REC tDPmin + t GTPmin - tDAmax
tID tDAmax + tGTAmax - tDPmin
tDO tDAmin + tGTAmin - tDPmax
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most applications, leaving R1
to be selected by the designer. Different steering arrangements may be used to select independent tone present
(tGTP) and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both
accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to
tailor system parameters such as talk-off and noise immunity.
Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 8.
6
Zarlink Semiconductor Inc.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]