LH531000B-S 데이터 시트보기 (PDF) - Sharp Electronics

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LH531000B-S

CMOS 1M (128K × 8) 3 V-Drive MROM

Sharp Electronics 

LH531000B-S

CMOS 1M MROM

A16 22

A15 1

A14 27

A13 26

A12 2

A11 23

A10 21

A9 24

A8 25

A7 3

A6 4

A5 5

A4 6

A3 7

A2 8

A1 9

A0 10

CE/OE/OE 20

CE

BUFFER

TIMING

GENERATOR

OE

BUFFER

MEMORY

MATRIX

(131,072 x 8)

COLUMN SELECTOR

SENSE AMPLIFIER

OUTPUT BUFFER

28 14

VCC GND

11 12 13 15 16 17 18 19

D0 D1 D2 D3 D4 D5 D6 D7

Figure 2. LH531000B-S Block Diagram

531000BS-2

PIN DESCRIPTION

SIGNAL

PIN NAME

NOTE

A0 – A16

Address input

D0 – D7

Data output

CE/OE/OE

Chip Enable input or

Output Enable input

1

NOTE:

1. Active level of CE/OE/OE is mask-programmable.

SIGNAL

VCC

GND

PIN NAME

Power supply

(2.6 V to 3.6 V)

Ground

NOTE

2

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