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CY7C1383F-100BGI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1383F-100BGI
Cypress
Cypress Semiconductor Cypress
CY7C1383F-100BGI Datasheet PDF : 29 Pages
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CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
deasserted and the IOs must be tri-stated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all
asserted active, (2) ADSC is asserted LOW, (3) ADSP is
deasserted HIGH, and (4) the write input signals (GW, BWE,
and BWX) indicate a write access. ADSC is ignored if ADSP is
active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core The information presented to DQ[A:D] will
be written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
provides an on-chip two-bit wraparound burst counter inside
the SRAM. The burst counter is fed by A[1:0], and can follow
either a linear or interleaved burst order. The burst order is
determined by the state of the MODE input. A LOW on MODE
will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst
sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE1, CE2, CE3 [2], ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min
2tCYC
0
Max
80
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Document #: 38-05544 Rev. *F
Page 8 of 29
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