ADN4690EBRZ-RL7(RevA) 데이터 시트보기 (PDF) - Analog Devices
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ADN4690EBRZ-RL7
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADN4690EBRZ-RL7 Datasheet PDF : 20 Pages
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Data Sheet
ADN4690E/ADN4692E/ADN4694E/ADN4695E
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages
VA (V)
VB (V)
2.4
0
0
2.4
3.475
3.325
3.425
3.375
−0.925
−1.075
−0.975
−1.025
Input Voltage, Differential
VID (V)
2.4
−2.4
0.15
0.05
0.15
0.05
Input Voltage, Common Mode
VIC (V)
1.2
1.2
3.4
3.4
−1
−1
Receiver Output
RO
H
L
H
L
H
L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
Symbol Min
Typ
Max
DRIVER
Maximum Data Rate
100
Propagation Delay
tPLH, tPHL
2
2.5
3.5
Differential Output Rise/Fall Time
tR, tF
2
2.6
3.2
Pulse Skew |tPHL − tPLH|
tSK
30
150
Part-to-Part Skew
Period Jitter, rms (One Standard Deviation)2
Peak-to-Peak Jitter2, 4
tSK(PP)
tJ(PER)
tJ(PP)
0.9
2
3
150
Disable Time from High Level
tPHZ
Disable Time from Low Level
tPLZ
Enable Time to High Level
tPZH
Enable Time to Low Level
tPZL
RECEIVER
Propagation Delay
tRPLH, tRPHL 2
Rise/Fall Time
tR, tF
1
Pulse Skew |tRPHL – tRPLH|
Type 1 Receiver (ADN4690E, ADN4692E) tSK
Type 2 Receiver (ADN4694E, ADN4695E) tSK
Part-to-Part Skew6
tSK(PP)
Period Jitter, rms (One Standard Deviation)2 tJ(PER)
Peak-to-Peak Jitter2, 4
4
7
4
7
4
7
4
7
6
2.3
100
300
300
500
1
4
7
Type 1 Receiver (ADN4690E, ADN4692E) tJ(PP)
Type 2 Receiver (ADN4694E, ADN4695E) tJ(PP)
Disable Time from High Level
tRPHZ
Disable Time from Low Level
tRPLZ
Enable Time to High Level
tRPZH
Enable Time to Low Level
tRPZL
200
700
225
800
6
10
6
10
10
15
10
15
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
3 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
4 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
5 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
6 HP4194A impedance analyzer or equivalent.
Unit Test Conditions/Comments
Mbps
ns
ns
ps
ns
ps
ps
ns
ns
ns
ns
See Figure 23, Figure 26
See Figure 23, Figure 26
See Figure 23, Figure 26
See Figure 23, Figure 26
50 MHz clock input3 (see Figure 25)
100 Mbps 215 − 1 PRBS input5
(see Figure 28)
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
See Figure 24, Figure 27
ns
CL = 15 pF (see Figure 29, Figure 32)
ns
CL = 15 pF (see Figure 29, Figure 32)
CL = 15 pF (see Figure 29, Figure 32)
ps
ps
ns
CL = 15 pF (see Figure 29, Figure 32)
ps
50 MHz clock input3 (see Figure 31)
100 Mbps 215 − 1 PRBS input5
(see Figure 34)
ps
ps
ns
See Figure 30, Figure 33
ns
See Figure 30, Figure 33
ns
See Figure 30, Figure 33
ns
See Figure 30, Figure 33
Rev. A | Page 5 of 20
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