CXB1567Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXB1567Q

Limiting Amplifier for Optical Fiber Communication Receiver

Sony Semiconductor 

CXB1567Q

2. Alarm block

As shown in Fig. 3, the alarm block requires external resistor REX1 for alarm level setting and peak hold

capacitor C3. When the resistance value provided for resistor REX1 is increased, the alarm setting level rises.

When the resistance value provided for REX2 is increased, the alarm setting level lowers. However, the voltage

of Pin 43 should always be higher than that of Pin 44. Normally, short-circuit Pin 44 to VEE (REX2 = 0). See

Fig. 5 for the alarm setting level. In the relationship between the alarm setting level and hysteresis width, the

hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4.

External capacitors C3 are used for input signal and alarm level peak hold capacitance. The C3 capacitance

value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The

deassert time becomes smaller by connecting resistor R10 between VEE and Pin 5 and resistor R11 between

VEE and Pin 6. The REX1 and C3 typical values are indicated below. (A capacitance of approximately 10pF is

built in Pins 5 and 6 respectively.)

REX1:

C3:

273Ω (VDAS = 3mVpp)

2000pF

VCCA

R7 1k

R8 100 R8 100

R7, R8, and R9 values

are typical values.

IC interior

IC exterior

R9 5k R9 5k

43

44

REX1

REX2

From

Limiting

amplifier

Peak hold

SD

SD

Peak hold

10p

VccA

6

R10

C3

10p

VccA

5

C3 R11

VEE

VEE

Fig. 3

VEE Vcc

Vcc VEE

24

VDAS → deassert level

20

High

VAS → assert level

level

16

Low

level

0

12

8

VDAS

VAS

Hysteresis width Input amplitude

4

20

log

(

VAS

VDAS

) = 6.0 dB

0

0

200

Fig. 4

– 11 –

VAS

VDAS

400

600

800

REX1 (Ω)

Fig. 5

1000

1200

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