STLC5460 데이터 시트보기 (PDF) - STMicroelectronics

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STLC5460

LINE CARD INTERFACE CONTROLLER

STMicroelectronics 

STLC5460

DESCRIPTION

The Line Card Interface Controller, STLC5460, is

a monolithic switching device for the path control

of up to 128 channels of 16, 32, 64 kbps band-

width. Two consecutive 64 kbps channels may

also be handled as a quasi single 128 kbps chan-

nel. For these channels, the LCIC performs non-

blocking space time switching between two serial

interfaces: the system interface (or PCM inter-

face) and the general component interface (GCI).

PCM interface can be programmed to operate at

different data rates between 2048 and 8192 kbps.

The PCM interface consists of up to four duplex

ports with a tristate indication signal for each out-

put line. The GCI interface can be selected to be

PCM interface at 2Mbit/s.

The LCIC can be programmed to communicate

with GCI compatible devices such as STLC3040

(SLIC), STLC5411 (U interface) and others. The

device manages the layer 1 protocol buffering the

Command/Indicate and Monitor channels for GCI

compatible devices.

Due to its capability to switch channels of different

BLOCK DIAGRAM

bandwidths, the STLC5460 can handle up to 16

ISDN subscribers with their 2B+D channel struc-

ture in GCI configuration, or up to 16 analog sub-

scribers. Since its interfaces can operate at differ-

ent data rates, the LCIC is an ideal device for

data rate adaptation between PCM interface up to

8Mb/s and GCI at 2Mb/s.

The device gives the possibility of checking the

correct communication inside the PBX or Public

Central Office providing :

- independentPCM delay setting

- PCM comparison function

- Pseudo RandomSequenceGeneratorandAnalyser.

Moreover, the LCIC is one of the key building

blocks for networks with either central, distributed

or mixed signaling and packet data handling ar-

chitectures associated with ST5451 (HDLC con-

troller).

The device is controlled by a standard 8 bit paral-

lel microprocessor interface with a multiplexed

address-data bus. The device may optionally be

controlled by separate address and data buses.

DESTINATION REG

(ADDRESS)

COMMAND REG

(DATA)

SOURCE REGISTER

(DATA)

COUNTERS

COMMAND MEMORY

194 WORDS OF 14 BITS

6 bits

COUNTERS

4 PCM

2 GCI

1 bit for 16 tristate

PARALLEL

SERIAL

SHIFTING

SPECIAL

SWITCH AT

16, 32, 64

KB/S

SWITCHING

MEMORY

194 BYTES

(4PCM+2GCI + 2

CHANNEL -INSERTION- =

128+64+2=194)

SERIAL

PARALLEL

SHIFTING

4 PCM

2 GCI

C/I, MON

TRANSMIT

16 INDIPENDENT

CONTROLLERS

EXTRACTION

2 x 64 Kbit

CHANNEL

D94TL160A

C/I, MON

RECEIVER

INSERTION

2 x 64 Kbit

CHANNEL

2/54

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