STLC5460 데이터 시트보기 (PDF) - STMicroelectronics

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STLC5460

LINE CARD INTERFACE CONTROLLER

STMicroelectronics 

MEMORY STRUCTURE AND SWITCHING

The LCIC contains three memories: Auxiliary

Memory (AM), Data Memory (DM) and Control

Memory (CM).

The Auxiliary Memory consists of one block di-

vided in four parts of 16 words.

This Auxiliary Memory is used for validated data

from Monitor and Command/Indicate Rx channels

and to transmit data to Monitor and Com-

mand/Indicate Tx channels.

The Data Memory buffers the data input from the

PCM and the GCI interface. It has a capacity of

128 + 64 time slots to buffer 4 PCM frame of 32

time slots and two GCI interfaces. It is written pe-

riodically once every 125 microseconds controlled

by the input counters associated to PCM interface

and to GCI interface. To perform the switching the

loopback function, this memory is read, random,

in accordance with the control memory

The Control Memory has a capacity of 128 + 64

words of 14 bits: 8 of data and 6 of code. The 14

bits are written random, via microprocessor in-

terface and read cyclically under the control of

the output counters associated to PCM interface

and GCI interface.

For control memory access and different func-

tions, three registers are provided:

destination register:

it contains the address of a specific location of

the control memory;

source register :

it contains the data (to be written or read) of the

Figure 4.

STLC5460

control memory corrisponding to the address indi-

cated by the destination register;

command register:

it contains the code (6 bits to be written or read)

of the control memory.

The content of command register defines the dif-

ferent capabilities: switching at 64 kb/s, 32 kb/s,

16 kb/s, loopback and also extraction/insertion

from the microprocessor interface.

A memory access using the actual command reg-

ister and source register is performed upon every

destination register write access. The processing

of the memory access takes at most 488ns.

MICROPROCESSOR INTERFACE

After Reset, the Microprocessor interface is in

non-multiplexed mode (Address bus and Data

bus must be non-multiplexed):

if ALE pin is hardwired at VSS, the Microproces-

sor interface is Motorola like, Address/Data are

non-multiplexed.

if ALE pin is hardwired at VDD the Microproces-

sor interface is Intel like, Address/Data are non-

multiplexed.

After Reset, as soon as two successive edges are

detected on ALE pin (Rising and falling edges) by

the circuit the Microprocessor interface switches

in multiplexed mode (Address bus and Data bus

must be multiplexed). The circuit is set automat-

ically in Motorola like or in Intel like mode.

For the circuit Address bus and Data bus multi-

plexed or not multiplexed, the difference between

Motorola like and Intel like mode is showed in fig. 4.

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