ACS8515(2001) 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8515
(Rev.:2001)

Line Card Protection Switch for SONET or SDH Network Elements

Semtech Corporation 

ACS8515 LC/P

ADVANCED COMMUNCIATIONS

FINAL

an acceptable level.

The registers reg sts_curr_inc_offset (address

0C, 0D, 07) report the frequency of the DPLL

with respect to the external TCXO frequency.

This is a 19 bit signed number with one LSB

representing 0.0003 ppm (range of +/- 80

ppm). Reading this regularly can show how the

currently locked source is varying in value e.g.

due to wander on its input.

The ACS8515 performs automatic frequency

monitoring with an acceptable input frequency

offset range of +/- 16.6 ppm. The ACS8515

DPLL has a programmable frequency limit of

+/- 80 ppm. If the range is programmed to be

> 16.6 ppm, the activity monitors should be

disabled so the input reference source is not

automatically rejected as out of frequency

range.

Output Clock Ports

The ACS8515 supports two SEC output clocks

on both TTL and PECL/LVDS ports and a pair

of secondary output clocks, ‘Frame-Sync’ and

‘Multi-Frame-Sync’. The two output clocks are

individually controllable. The ‘Frame-Sync’ and

‘Multi-Frame-Sync’ are derived from the main

SEC clock. The frequencies of the output clock

are selectable from a range of pre-defined spot

frequencies, and a variety of output

technologies are supported, as defined in Table

5.

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Figure 1: Minimum Input Jitter Tolerance for inputs supporting G.783 compliant sources

STM

level

Peak to peak amplitude

(unit Interval)

Frequency (Hz)

A0 A1 A2 A3 A4 F0 F1 F2

F3

F4

F5

F6 F7 F8 F9

STM-1 2800 311 39 1.5 0.15 12u 178u 1.6m 15.6m 0.125 19.3 500 6.5k 65k 1.3m

Table 3: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.783 compliant sources

Revision 2.05/Jan 2001 ã2001 Semtech Corp

10

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