ACS8515(2001) 데이터 시트보기 (PDF) - Semtech Corporation
부품명
상세내역
제조사
ACS8515 Datasheet PDF : 47 Pages
| |||
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
Pin Descriptions
Power
PIN
SYMBOL
IO TYPE
FINAL
NAME/DESCRIPTION
8, 9, 12
VD+
P
-
Supply voltage: Digital supply to gates in analog section, +3.3
Volts. +/- 10%
22
VDD_DIFF
P
-
Supply voltage: Digital supply for differential output pins 19 &
20, +3.3 Volts. +/- 10%
VDD5: Digital supply for +5 Volts tolerance to input pins. Connect
27
VDD5
P
-
to +5 volts (+/- 10%) for clamping to +5 v. Connect to VDD for
clamping to +3.3 v. Leave floating for no clamping, input pins
tolerant up to +5.5 v.
32, 36, 38,
39, 45, 46,
VDD
P
- Supply voltage: Digital supply to logic, +3.3 Volts. +/- 10%
54, 57
4
VA1+
P
-
Supply voltage: Analog supply to clock multipying APLL, +3.3
Volts. +/- 10%
14
VA2+
P
-
Supply voltage: Analog supply to output APLL, +3.3 Volts. +/- 10%
7, 10, 11,
31, 40, 53,
DGND
P
-
Supply Ground: Digital ground for logic
58
21
GND_DIFF
P
-
Supply Ground: Digital ground for differential output pins 19 &
20
1, 3, 15
AGND
P
-
Supply Ground: Analog ground
No connections
PIN
SYMBOL IO TYPE
NAME/DESCRIPTION
55, 59
NC
-
-
Not Connected: Leave to Float
2, 16, 60,
61, 62, 63
IC
-
-
Internally Connected: Leave to Float
37
IC
-
-
Internally connected: Leave to Float. Reserved for JTAG control
reset input on next revision
41
IC
-
-
Internally connected: Leave to Float. Reserved for JTAG test mode
select input on next revision
49
IC
-
-
Internally connected: Leave to Float. Reserved for JTAG
boundary scan clock input on next revision
50
IC
-
-
Internally connected: Leave to Float. Reserved for JTAG serial test
data output on next revision
51
IC
-
-
Internally connected: Leave to Float. Reserved for JTAG serial test
data input on next revision
Revision 2.05/Jan 2001 ã2001 Semtech Corp
4
www.semtech.com
Share Link: 