ACS8515(2001) 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8515
(Rev.:2001)

Line Card Protection Switch for SONET or SDH Network Elements

Semtech Corporation 

ACS8515 LC/P

ADVANCED COMMUNCIATIONS

Others

FINAL

PIN

SYMBOL

IO TYPE

NAME/DESCRIPTION

5

INTREQ

O

-

Interupt request: Software Interrupt enable

6

REFCLK

I

TTL

Reference clock: 12.8 MHz (refer to section headed Local

Oscillator Clock)

13

SRCSW

I

TTLD Source switching: Force fast source switching on SEC1 and SEC2

17

FrSync

O

TTL

Output reference: 8 kHz Frame Sync, 50:50 mark/space ratio

output

18

MFrSync

O

TTL

Output reference: 2 kHz Multi-Frame Sync, 50:50 mark/space

ratio output

19

20

O1POS

O1NEG

O

LVDS/

PECL

Output reference: Programmable, default 38.88 MHz LVDS

23

24

SEC1_POS

SEC1_NEG

I

LVDS/

PECL

Input reference: Programmable, default 19.44 MHz LVDS

25

26

SEC2_POS

SEC2_NEG

I

PECL/

LVDS

Input reference: Programmable, default 19.44 MHz PECL

28

Sync2k

I

TTLD Multi-Frame Sync 2 kHz: Multi-Frame Sync input

29

SEC1

I

TTLD Input reference: Programmable, default 8 kHz

30

SEC2

I

TTLD Input reference: Programmable, default 8 kHz

33

IC

-

-

Internally connected: Connect to GND. Reserved for Slave Multi-

frame sync 2 kHz input on next revision.

34

SEC3

I

TTLD

Input reference: External standby reference clock source,

programmable, default 19.44 MHz

35

IC

-

-

Internally connected: Connect to GND. Reserved for external

standby 2 kHz Multi-frame sync input on next revision.

42

CLKE

I

TTLD

SCLK edge select: SCLK active edge select, CLKE=1 selects

falling edge of SCLK to be active

43

SDI

I

TTLD Microprocessor interface address: Serial data input

44

CSB

I

TTLU

Chip select (active low): This pin is asserted Low by the

microprocessor to enable the microprocessor interface

Address Latch Enable: default Serial data clock. When this pin

47

SCLK

I

TTLD transitions from high to low, the address bus inputs are latched

into the internal registers

48

PORB

I

TTLU

Power on reset: Master reset. If PORB is forced Low, all internal

states are reset back to default values

Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor

Revision 2.05/Jan 2001 ã2001 Semtech Corp

5

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