ACS8515(2001) 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8515
(Rev.:2001)

Line Card Protection Switch for SONET or SDH Network Elements

Semtech Corporation 

ACS8515 LC/P

ADVANCED COMMUNCIATIONS

FINAL

PECL and LVDS ports support the spot clock

frequencies listed above plus 155.52 MHz. The

choice of PECL or LVDS compatibility is

programmed via the cnfg_differential_inputs

register.

Unused PECL/LVDS differential inputs should

be fixed with one input high (VDD) and the other

input low (GND), or set in LVDS mode and left

floating, in which case one input is internally

pulled high and the other low.

Input Wander and Jitter Tolerance

The ACS8515 is compliant to the requirements

of all relevant standards, principally ITU

Recommendation G.825, ANSI T1.101-1994

and ETS 300 462-5 (1997).

All reference clock inputs have a tight frequency

tolerance but a generous jitter tolerance. Pull-

in, hold-in and pull-out ranges are specified for

each input port in Table 2. Minimum jitter

tolerance masks are specified in Figures 1 and

2, and Tables 3 and 4, respectively. The

ACS8515 will tolerate wander and jitter

components greater than those shown in Figure

1 and Figure 2, up to a limit determined by a

combination of the apparent long-term

frequency offset caused by wander and the

eye-closure caused by jitter (the input source

will be rejected if the offset pushes the

frequency outside the hold-in range for long

enough to be detected, whilst the signal will

also be rejected if the eye closes sufficiently to

affect the signal purity). The ‘8klocking’ mode

should be engaged for high jitter tolerance

according to these masks.

All reference clock ports are monitored for

quality, including frequency offset and general

activity. Single short-term interruptions in

selected reference clocks may not cause

rearrangements, whilst longer interruptions, or

multiple, short-term interruptions, will cause

rearrangements, as will frequency offsets which

are sufficiently large or sufficiently long to cause

loss-of-lock in the phase-locked loop. The failed

reference source will be removed from the

priority table and declared as unserviceable,

until its perceived quality has been restored to

Jitter

Tolerance

Frequency Monitor

Acceptance Range

Freq u en cy

Acceptance Range

(Pull-in)

Freq u en cy

Acceptance

Range (Hold-in)

Freq u en cy

Acceptance Range

(Pull-out)

G.703

G.783

G.823

GR-1244-CORE

+/- 16.6 ppm

+/- 4.6 ppm

(see Note 1)

+/- 9.2 ppm

(see Note 2)

+/- 4.6 ppm

(see Note 1)

+/- 9.2 ppm

(see Note 2)

+/- 4.6 ppm

(see Note 1)

+/- 9.2 ppm

(see Note 2)

Table 2: Input Reference Source Jitter Tolerance.

Notes for Table 2.

Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the

external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.

Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal

frequency of 12.8 MHz.

Note 3. The power up default PDLL range is as stated in note 2, but the range is also programmable from 0 to 80 ppm

in 0.08 ppm steps.

Revision 2.05/Jan 2001 ã2001 Semtech Corp

9

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