ACS8515 데이터 시트보기 (PDF) - Semtech Corporation
부품명
상세내역
제조사
ACS8515 Datasheet PDF : 50 Pages
| |||
ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
Table 3 (continued).
PIN
SYMBOL
IO TYPE
NAME/DESCRIPTION
FINAL
52
SDO
O
TTLD Microprocessor inter face address: Serial data output
56
O2
O
TTL Output reference: 19.44 MHz fixed
SONETSDHB: SONET or SDH frequency select: sets the initial
power-up state (or state after a PORB) of the SONET/SDH
64
SONSDHB
I
TTLD
frequency selection registers, addr 34h, bit 2 and addr 38, bits 5
and 6. When low SDH rates are selected (2.048 MHz etc) and
when set high SONET rates are selected (1.544 MHz etc). The
register states can be changed after power up by software.
Functional Description
The ACS8515 is a highly integrated, single-chip
solution for ‘hit-less’ protection switching of SEC
clocks from Master and Slave SETS clock cards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the
inputs and will implement automatic system
protection switching for Master/Slave SEC clock
failure. The standby SEC clock will be selected
if both the Master and Slave input clocks fail.
The selection of the Master/Slave input can
also be forced by a Force Fast Switch pin.
The ACS8515 includes an SPI compatible serial
microprocessor port, providing access to the
configuration and status registers for device
setup.
Local Oscillator Clock
The Master system clock on the ACS8515
requires an external clock oscillator of frequency
12.80 MHz. The exact clock specification is
dependent on the quality of Holdover
performance required in the application.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card - e.g. 8 kHz
distributed on the back plane and 19.44 MHz
generated on the line cards.
The ACS8515 has three SEC clock inputs
(Master, Slave and Standby) and a single Multi-
Frame Sync input, for synchronising the frame
and multi-frame sync outputs.
In most Line Card protection switching
applications where there is a high chance that
at least one SEC reference input will be
available, the long term stability requirement
for Holdover is not appropriate and an
inexpensive crystal local oscillator can be used.
In other applications where there may be a
requirement for longer term Holdover stability
to meet the ITU standards for Stratum 3, a
higher quality oscillator can be used.
The ACS8515 generates two SEC clock outputs
via PECL/LVDS and TTL ports, with spot
frequencies from 1.544/2.048 MHz up to
311.04 MHz. The ACS8515 also provides an
8 kHz Frame Sync and 2 kHz Multi-Frame Sync
output clock.
The ACS8515 has a high tolerance to input
jitter and wander. The jitter/wander transfer is
programmable (0.1 Hz up to 20 Hz cut-off
points).
Please contact Semtech for information on
crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less
important than the stability since any frequency
offset can be compensated by adjustment of
register values in the IC. This allows for
calibration and compensation of any crystal
frequency variation away from its nominal value.
Revision 2.01/December 2005 Semtech Corp.
7
www.semtech.com
Share Link: 